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| March 1996 NDS355N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features 1.6A, 30V. RDS(ON) = 0.125 @ VGS = 4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. _______________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage T A = 25C unless otherwise noted NDS355N 30 20 (Note 1a) Units V V A Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1b) (Note 1a) 1.6 10 0.5 0.46 -55 to 150 W Operating and Storage Temperature Range C THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to -Case (Note 1a) (Note 1) 250 75 C/W C/W (c) 1997 Fairchild Semiconductor Corporation NDS355N Rev. D1 Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 A VDS = 24 V, VGS = 0 V TJ=125C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 12 V, VDS = 0 V VGS = -12 V, VDS= 0 V VDS = VGS, ID = 250 A TJ=125C Static Drain-Source On-Resistance VGS = 4.5 V, ID = 1.6 A TJ=125C VGS = 10 V, ID = 1.9 A ID(ON) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V VDS = 5 V, ID = 1.6 A VDS = 10 V, VGS = 0 V, f = 1.0 MHz 6 3.5 1 0.5 1.6 1.3 30 1 10 100 -100 V A A nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage 2 1.5 0.125 0.25 0.085 A S V DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) 245 130 20 pF pF pF SWITCHING CHARACTERISTICS Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 6 15 14 12 4 30 30 25 10 5 1 2 ns ns ns ns nC nC nC VDS = 10 V, ID = 1.6 A, VGS = 5 V 3.5 NDS355N Rev. D1 Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS ISM VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. Maximum Continuous Source Current Maximum Pulse Source Current (Note 2) Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.6 A 0.8 0.6 6 1.2 A A V PD (t) = R J A (t) TJ -TA = TJ -TA R J C CA +R (t) = I 2 (t) x RDS(ON ) D TJ Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. NDS355N Rev. D1 Typical Electrical Characteristics 12 2 V GS =10V I D , DRAIN-SOURCE CURRENT (A) 6.0 5.0 4.5 R DS(on) , NORMALIZED VGS =3.5V DRAIN-SOURCE ON-RESISTANCE 9 4.0 1.5 4.0 6 4.5 5.0 1 3.5 3 6.0 10 3.0 0 0 1 2 3 V DS , DRAIN-SOURCE VOLTAGE (V) 4 0.5 0 3 I D 6 , DRAIN CURRENT (A) 9 12 Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Gate Voltage and Drain Current 1.6 3 DRAIN-SOURCE ON-RESISTANCE 1.4 V GS =4.5V R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D = 1.6A V GS = 4.5V 2.5 R DS(ON) NORMALIZED , 1.2 T J = 125C 2 1 1.5 25C -55C 0.8 1 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 0.5 0 2 4 6 8 I D , DRAIN CURRENT (A) 10 12 Figure 3. On-Resistance Variation with Temperature Figure 4. On-Resistance Variation with Drain Current and Temperature 10 1.2 V DS = 10V 8 I D , DRAIN CURRENT (A) 125C GATE-SOURCE THRESHOLD VOLTAGE (V) TJ = -55C 25C VDS = V GS 1.1 I D = 250A Vth , NORMALIZED 1 6 0.9 4 0.8 2 0.7 0 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 6 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature NDS355N Rev. D1 Typical Electrical Characteristics (continued) 1.15 DRAIN-SOURCE BREAKDOWN VOLTAGE (V) 20 I D = 250A I , REVERSE DRAIN CURRENT (A) 1.1 10 VGS = 0V BV DSS , NORMALIZED 1 1.05 T J = 125C 25C 0.1 -55C 1 0.95 0.01 0.9 -50 -25 0 T J 25 50 75 100 125 , JUNCTION TEMPERATURE (C) 150 175 S 0.001 0.2 0.4 0.6 0.8 1 1.2 1.4 VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature Figure 8. Body Diode Forward Voltage Variation with Current and Temperature 500 300 200 CAPACITANCE (pF) 10 C iss V GS , GATE-SOURCE VOLTAGE (V) 8 I D = 1.6A VDS = 5V C oss 100 10 6 15 50 30 4 f = 1 MHz V GS = 0 V 0.1 0.2 0.5 1 2 5 10 C rss 2 0 30 0 1 2 3 4 5 6 7 V DS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics VDD t d(on) t on tr 90% t off t d(off) 90% tf V IN D RL V OUT DUT Output, Vout VGS 10% 10% 90% R GEN Inverted G Input, Vin S 10% 50% 50% Pulse Width Figure 11. Switching Test Circuit Figure 12. Switching Waveforms NDS355N Rev. D1 Typical Electrical Characteristics (continued) 8 20 , TRANSCONDUCTANCE (SIEMENS) -55C 6 10 25C I D , DRAIN CURRENT (A) 2 1 0.5 R ( DS ) ON Lim it 10 1m 10 10 s 0u s T J = 125C 4 ms 2 0.1 V GS = 10V SINGLE PULSE T A = 25C 0m s 1 10 s s DC g FS VDS = 5V 0 0 2 4 6 8 10 12 I D , DRAIN CURRENT (A) D 0.01 0.1 1 V DS 2 5 10 20 30 50 , DRAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature Figure 14. Maximum Safe Operating Area 1 0.5 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 0.2 0.1 0.05 0.02 0.01 P(pk) R JA (t) = r(t) * RJA R = 250 C/W JA t1 Single Pulse t2 TJ - T A = P * R JA (t) Duty Cycle, D = t1 /t2 0.001 0.01 0.1 t1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve Note : Characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS355N Rev. D1 |
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